Microprocessors and other components in computer systems often have logic circuits which allow them to perform logical operations. As performance requirements increase, faster logic circuits are required in the microprocessors and other components to provide the requisite level of performance. One manner of enhancing performance involves reducing the number of gate delays. One prior logic circuit, the domino logic circuit, performs a logical operation in one gate delay. With an AND operation, the domino logic circuit precharges a node to a high potential. The inputs of the domino logic circuit are each coupled to a gate of an n type field effect transistor. The transistors are coupled in series to the node and ground potential. When all of the inputs of the domino logic circuit have a logical-one signal state, thus satisfying the AND condition, all of the n type transistors are in the ON state. A conductive path to ground potential is created and the node discharges from a high potential to a low potential. When one of the inputs of the domino logic circuit has a logical-zero signal state, one of the transistors in series remains in the OFF state. A conductive path to ground potential is not created and the node does not discharge from high potential to low potential. The node instead remains at the high potential. An OR operation can also be implemented in the domino logic circuit by arranging the n type transistors in parallel between the node and ground potential. In this mariner, any input with a logical-one signal state can discharge the node from high potential to ground potential. Other logical operations can also be implemented using combinations of AND and OR operations.
However, with increasing performance requirements of microprocessors and other components, logic circuits with further enhanced performance capabilities are required.
Thus, what is needed is a faster logic circuit.